1. Field of the Invention
The invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating a dual damascene.
2. Description of the Related Art
When following the trend of semiconductor device size reduction, the wiring lines of the interconnect structure are necessarily formed increasingly closer to each other. Therefore, the dielectrics with a low dielectric constant (low k dielectrics) currently fills between the wiring lines to prevent parasitic capacitance, which occurs between the wiring lines when the distance between the wiring lines is reduced.
During the dual damascene manufacturing process, the trench and via profile are heavily affected due to the poor etching selectivity between the photoresist and the low k dielectrics while removing the photoresist layer by oxygen plasma Therefore, complicated processes and structure are required for dual damascene in order to avoid the aforementioned problems. FIGS. 1A-1E schematically illustrate fabrication of a dual damascene structure according to prior art. Referring to FIG. 1A, a barrier layer 104, a low k dielectric layer 106, a hard mask layer 108 and an anti-reflection layer 110 are successively formed on a semiconductor substrate 102 having a wiring line 100. The hard mask layer 108 and the anti-reflection layer 110 have a thickness of about 1000-2000 angstroms and 600 angstroms, respectively. Thereafter, the anti-reflection layer 110 is patterned by photolithography with a photoresist layer (not shown) to expose the hard mask layer 108, and then the photoresist is removed by oxygen plasma. The presence of the hard mask layer 108 can protect the low k dielectric layer 106 from being destroyed by oxygen plasma. Using the patterned anti-reflection layer 110 as an etching mask, an opening 112 is formed to expose the low k dielectric layer 106 over the wiring line 100 by anisotropically etching the hard mask layer 108.
Referring to FIG. 1B, a low k dielectric layer 114, a hard mask layer 116 and an anti-reflection layer 118 are successively formed on the anti-reflection layer 110. The steps of patterning the anti-reflection layer 118, removing the photoresist layer and using the anti-reflection layer 118 as an etching mask to define the hard mask layer 116 is then repeated as described above. Accordingly, openings 120a, 120b are formed within the hard mask layer 116a to expose a portion of the low k dielectric layer 114, as shown in FIG. 1C.
Using the hard mask layer 116a as a mask, isotropic etching is then performed on the low k dielectric layer 114, 106 until exposing the barrier layer 104 and the anti-reflection layer 110. As a result, a wiring line opening 122a, a via hole 124 and a trench 122b are formed, as illustrated in FIG. 1D. Thereafter, the exposed barrier layer 104 is removed to expose the wiring line 100, as shown in FIG. 1E. The wiring line opening 122a, the via hole 124 and the trench 122b are filled with a metal layer to form wiring lines 126a, 126b and a via 124.
During the fabrication of dual damascene, the barrier layer 104, the anti-reflection layer 110 and the hard mask layer 108, 116a are dielectrics with high dielectric constant, such that the effective capacitance of the dual damascene structure is increased. As a result, the advantage of the low k dielectrics 106, 114 is canceled out and the parasitic capacitance between the wiring lines cannot be diminished.
In addition, the photoresist layer (not shown) for patterning the anti-reflection layer 110, 118 and hard mask layer 108, 116 is removed by oxygen plasma and oxygen plasma easily reacts with low k dielectric layer 114, 106. The reaction between the low k dielectric layer 114, 106 and the oxygen plasma not only changes the property of the low k dielectric layer 114, 106 such that the dielectric constant thereof is increased, but also destroys the sidewall profile of the opening 122a, 122b within the low k dielectric layer 114, 106 due to the lateral etching of the oxygen plasma.
Moreover, the interconnect structure of dual damascene as described above in FIG. 1E is achieved by a series of steps including deposition, photolithography and etching. The complicated processes require a large amount of cycle time and increase manufacturing cost.